This invention relates, in general, to semiconductor devices and, more particularly, to a method of manufacturing refractory silicide gates and device interconnections having particular applicability in high speed integrated circuits.
In an article entitled "Beam-Lead Technology" by M. P. Lepselter which appeared in the Bell System Journal, Vol. XLV, No. 2, February 1966, there is described a process for fabricating beam-lead transistors where the leads form both the structural and electrical function. The contact and the subsequent formation of a lead consisting of sputtered titanium and platinum layers followed by a layer of electroformed gold is described. This represents an early attempt by the prior art to lower the resistance of the interconnecting leads. However, as the state of the integrated circuit art progressed, to achieve higher packing densities and reduced manufacturing costs, it became obvious that the process proposed in the above Lepselter article would be unacceptable since the leads occupied excessive areas of real estate and the added step of sputtering the titanium and platinum layers as well as electroforming the gold, raise the costs of the furnished device beyond acceptable limits.
An alternative to the use of elemental metallic leads of the early prior art, one current technique for producing lower resistance interconnecting leads, necessary in high density integrated circuits, involves the use of doped polysilicon interconnects. In addition, to achieve still higher packing densities, buried contacts have also found wide use. When used in NMOS technology, few difficulties are encountered using the doped polysilicon technique since both the polysilicon leads and the bulk silicon are doped with N-type impurities. However, when processing CMOS devices where it is necessary to have a lead interconnecting both a P channel and an N channel device, there are only relatively few techniques which will satisfactorily interconnect the devices without encountering the formation of an objectionable PN junction. One such method is described in Application No. 118,049, filed Feb. 4, 1980, by D. J. Tanguay, et al., entitled "BURIED CONTACT FOR COMPLEMENTARY MOS DEVICES" and assigned to the same assignee as the subject application, overcomes the difficulties of the prior art by utilizing a polysilicon line, doping the line with whatever type dopant conveniently suits the processing step, allowing the undesired junction to be formed and, thereafter, providing the junction with an electrical short circuit in the form of a polysilicided section which extends across and electrically short circuits the junction.
Still another prior art method utilized to overcome the prior art shortcomings is embodied in Application No. 127,046, filed Mar. 4, 1980, by C. E. Weitzel, et al., entitled "LOW SURFACE RESISTANCE MOSFET DEVICE AND METHOD OF MAKING SAME" and assigned to the same assignee as the subject application in which a portion of the surfaces of the drain and source regions, as well as a portion of the gate surface, is silicided in order to reduce the sheet resistance thereof. Thereafter, metallic ohmic contacts may be easily made to any of the portions of the now silicided areas.
As will be obvious to those skilled in the art, the common thread running through the prior art resides in the deposition of a refractory metal layer on a previously formed layer of silicon in order to produce, after treatment, a silicided region. The difficulties encountered with such a process come about when, for example, after treatment the user is left with either an excess of refractory metal or an excess of silicon. Thereafter, the excess refractory metal must be removed within a short period of time in order to prevent the formation of an undesirable oxide and in the case of excess silicon (insufficient refractory metal) one does not achieve the desired result. Accordingly, it becomes extremely difficult to achieve consistent results using the prior art methods.